A technique in which each functional block is mounted for each normal block in which an integrated circuit device is standardized by a fixed area is described in Japanese Patent Application Laid-Open Publication No. 2003-23090 (Patent Document 1).
Also, a technique in which an additional pattern in a triangular shape is formed on an end portion of a wiring pattern in a connection margin for stitching exposure is disclosed in Japanese Patent Application Laid-Open Publication No. H11-67639 (Patent Document 2).
Further, a technique of manufacturing an integrated circuit in which a dividing process from a large chip into a plurality of sub chips is particularly creatively designed so that a common mask can be used between the plurality of sub chips in most steps and a mask for a few steps only is separately prepared is disclosed in Japanese Patent Application Laid-Open Publication No. H5-47622 (Patent Document 3).